Overview
The Invensys Triconex 3003, also cataloged as the 3003 Enhanced Main Processor Module II, executes system diagnostics and user-written control programs within Tricon v9.6 and later systems. It independently communicates with the I/O subsystem through the TMR architecture using the Tribus communication interface.
Hardware Specifications
| Parameter | Specification |
|---|---|
| Model | 3003 |
| Brand | Invensys Triconex |
| Product Type | Enhanced Main Processor Module II (EMPII) / Main Processor (MP) |
| System Platform | Tricon v9.6 and later |
| Primary Function | System diagnostics and user-written control program execution |
| CPU | Motorola MPC860, 32-bit, 50 MHz |
| DRAM | 16 MB, non-battery backed-up |
| SRAM | 32 KB, battery backed-up |
| Flash PROM | 6 MB |
| Tribus Communication Rate | 25 Mbit/s |
| Tribus Protection | 32-bit CRC protected |
| DMA | Fully isolated 32-bit DMA |
| Safety Architecture | Triple Modular Redundant (TMR) |
| Safety Integrity Level | SIL 3 |
| Main Processor Requirement | Three Main Processors per Tricon main chassis |
| Physical Construction | Industrial-grade enclosure with heavy-duty edge connectors |
TMR Main Processor and Tribus Communication
The 3003 functions as a Main Processor within the Tricon TMR architecture. Each Tricon system requires three Main Processors in the main chassis according to the supplied specifications.
The Motorola MPC860 provides the stated 32-bit processing platform at 50 MHz. The processor executes system diagnostics and user-written control programs while communicating with the I/O subsystem.
The Tribus interface operates at 25 Mbit/s and uses 32-bit CRC protection. The supplied data also specifies fully isolated 32-bit DMA, which defines the stated data-transfer architecture between processor and system resources.
The 3003 provides 16 MB of non-battery-backed DRAM, 32 KB of battery-backed SRAM, and 6 MB of Flash PROM. These memory types serve different storage and execution functions within the processor hardware.
The supplied data identifies SIL 3 compliance and TMR operation. Therefore, system-level safety configuration must retain the specified three-processor arrangement.
Frequently Asked Questions
Q: How many 3003 Main Processors are required in a Tricon main chassis?
A: The supplied specifications state that three Main Processors must be installed in the main chassis of every Tricon system to maintain the TMR architecture.
Q: What is the Tribus communication rate of the 3003?
A: The specified Tribus communication rate is 25 Mbit/s with 32-bit CRC protection and fully isolated 32-bit DMA.
Q: What memory does the 3003 provide?
A: The supplied data specifies 16 MB non-battery-backed DRAM, 32 KB battery-backed SRAM, and 6 MB Flash PROM.
Field Installation Guidelines
Install three 3003 Main Processors in the designated Tricon main chassis positions according to the system hardware configuration. Confirm the processor slot assignments before installation.
Inspect the heavy-duty edge connectors for contamination, mechanical damage, or improper alignment. Seat each module evenly and confirm full connector engagement before applying power.
Maintain the documented TMR processor arrangement. Do not operate the system with a processor configuration that differs from the approved Tricon hardware architecture.
Route processor and communication wiring separately from high-voltage power conductors and high-current switching circuits where practical. Follow the installed Tricon system grounding and shielding requirements for connected communication wiring.
Before commissioning, verify the installed processor configuration, memory hardware, chassis connections, and Tribus communication path. Confirm the applicable hardware revision and system software compatibility before executing user control programs.
Do not infer operating temperature, power consumption, weight, dimensions, or additional electrical ratings from other Tricon processor models. Confirm those parameters from the applicable hardware documentation or nameplate.
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